Control device with adjusting pulse width modulation function and the backlight module thereof

ABSTRACT

A voltage converter with a sampling-hold and integrating circuit is provided herein. According to the minimum different value generated by the practical status of each of the illuminant channels in the LED backlight module, the sampling-hold and integrating circuit will generate an superposition voltage and the voltage converter can output different PWM signal to drive each of the illuminant channels in the backlight module. When the sampling-hold and integrating circuit of the voltage converter and the control device with adjusting pulse width function are embedded together to provide to the LED backlight module, the power saving is more convenient.

The current application claims a foreign priority to the patentapplication of Taiwan No. 100130184 filed on Aug. 23, 2011.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is an adjusting device of the light emitting diode(LED) backlight module, and more particularly is to provide the mostsuitable pulse width modulation (PWM) in each of the channels of the LEDbacklight module before driving the LED backlight module.

2. Description of the Prior Art

The backlight module of the large scale Liquid Crystal Display (LCD) TVis using Cold Cathode Fluorescent Lamp (CCFL) or Light Emitting Diode(LED) to be the light source. Because the CCFL light tube implements themercury (HG) to be the illuminant light source, the mercury will causethe environmental protection problem during manufacturing and recycling.In addition, the CCFL tube must be isolated from air to increase thelife time. The LED technology is well developed and the illuminantefficiency is better than the CCFL tube and the LED technology isflexible and easy in color and illuminant control. Therefore, the directbacklight module made by LED is going to substitute the CCFL tube to bethe backlight module in LCD.

Please referring to FIG. 1A, it is a view illustrating a directbacklight module made by conventional LED. As shown in FIG. 1A, thedirect backlight module 400 is made by several illuminant channels(401-40 n, n is an integral) and each of the illuminant channels 401includes many LEDs 500. One of the significant drawbacks in the LEDdirect backlight module is the illuminant of the individual LEDs is notall the same, especially when red light, green light and blue light LEDsare together to generate white light. The color temperature of the whitelight is difficult to control. Moreover, the illuminant of the differentcolor light LED includes different temperature reaction. When LED hasbeen worked for a period time, the temperature of LED is increased astime goes on and the illuminant difference in each of the LED isincreased. For example, when the room temperature is increased over 80°C., the attenuation of the red light LED is more than the blue lightLED, and the attenuation of the blue light LED is more than the greenlight LED. Therefore, the direct backlight module made by several LEDsis easily affected by the different color LED so as to vary the colortemperature and the even illumination.

Moreover, in prior art, the analog driving circuit of the LED isconfigured to drive the direct backlight module transmits the controlsignal generated by the triangle wave generator and the amplifier to theDC-DC converter 600 (such as buck type or boost type DC-DC converter) soas to control turning the LED on or off. When the DC-DC converter 600 isconfigured to drive the LED array, the lumen in each of the LED isvaried in accordance with the difference of the forward bias. Therefore,it is difficult to control the color temperature and the illuminant ofthe LED array.

In addition, in order to determine the voltage variation in each of theLED, some technologies utilizes the look-up table. However, thosemethods are required lots of memory, and those technologies are hard tobe embedded in one chip.

Now, please referring to FIG. 1B, it is a block diagram illustrating theDC-DC converter of the LED backlight module in prior art. As shown inFIG. 1B. The voltage signal transmitted to the output voltage illuminantdevice 400 is that the pulse width modulation input and the outputvoltage are modulated by the current control circuit 53; the pulse widthmodulation (PWM) signal in each of the light channel is controlled to betransmitted to the select circuit 52 so as to select a pulse high signalat minimum conduction and at final, one voltage output (Vout) istransmitted to the illuminant device 400. Therefore, when the PWM signalis turned on at duty cycle, each of the light channels absorbs thecurrent at the output voltage V (Vout). When the PWM signal is turnedoff at duty cycle, each of the light channels is closed. In prior art, aclamp circuit (not shown) is used to keep providing a stable voltagewhen the duty cycle is off. According to the description above, the PWMsignal generated by the DC-DC converter and used to control each of thelight channels uses the same frequency, the same phase and the same dutycycle to drive the illuminant device 400, as shown in FIG. 1C (theequivalent circuit of the illuminant device in FIG. 1B). Obviously, theequivalent circuit in FIG. 1C is not able to change the duty cycle andthe phase of the PWM signal. It is not necessary to drive the illuminantdevice 400 by the PWM signal with the same duty cycle and the samephase. The better method is to provide proper PWM signal in accordancewith the actual variation at each of the light channels.

Moreover, in order to overcome the problem that different phase in FIG.1C cannot be solved; another conventional technique is to include a VFBresistor and a holding circuit in FIG. 1D so as to change the phase ofthe PWM signal. Therefore, the illuminant device 400 includes the PWMsignal with different phase to drive the illuminant device. However, thedifficulty of the circuit design is increased and a feedback pin isadded in the chip, so the manufacture cost is increased.

SUMMARY OF THE INVENTION

In order to solve the drawbacks described above, the main object of thepresent invention is to provide a voltage converter with a sampling-holdand integrating circuit. According to the minimum different valuegenerated by the practical status of each of the illuminant channels inthe LED backlight module, the sampling-hold and integrating circuit willgenerate a superposition voltage by superposition theory and the voltageconverter can output an analog signal to drive each of the illuminantchannels in the backlight module. When the sampling-hold and integratingcircuit of the voltage converter and the control device with adjustingpulse width function are embedded together to provide to the LEDbacklight module, the power saving is more convenient.

Another object of the present invention is to provide a control devicewith adjusting pulse width function. According to the information of theadjusting loops and the design of the sampling-hold and integratingcircuit, the control device in the present invention is able to adjustthe PWM signal in accordance with the practical status of each of theilluminant channels. Therefore, each of the illuminant channels isdriven in accordance with the PWM signal with the same frequency,different phase and different duty cycle. The control device in thepresent invention is not only configured to provide proper current toeach of the illuminant devices to avoid the inconsistent of theilluminant or color because of the bad driving of the LED backlightmodule but also to drive the illuminant device by the PWM signalgenerated by the sampling-hold and integrating circuit. The power savingis more convenience.

One another object of the present invention is to provide a module unitwith adjusting pulse width function. The module unit is configured toconvert the analog PWM signal to be digital PWM control signal. Thedigital PWM control signal is executed by the adjusting unit andtransmitted to the constant current regulator so as to control thecurrent consistent of the LED backlight module.

One object of the present invention is to provide a control device withadjusting pulse width function. According to the information of theadjusting loops, the control device can adjust the PWM signal inaccordance with the practical status of each of the illuminant channelsin the LED backlight module and provide proper current in each of theilluminant channels. Therefore, the PWM signal in the present inventionwith the same frequency, different phase and different duty cycle can beused to drive each of the illuminant channels in the backlight module soas to avoid the inconsistent of the illuminant or color because of backdriving of the LED backlight module.

According objects described above, a voltage converter includes one endconnected to a constant current regulator and the constant currentregulator is connected to a PWM signal of the illuminant channels, andthe voltage converter includes a minimum voltage selector, asampling-hold and integrating circuit and a boost circuit. The minimumvoltage selector includes an input end respectively connected to a PWMsignal of the illuminant channels and a plurality of first referencevoltages corresponding to the plurality of illuminant channels, and anoutput end outputs a pulse high signal at the minimum conduction. Thesampling-hold and integrating circuit includes a first input end and asecond input end, and the first input end is connected to the pulse highsignal of the minimum voltage selector and outputs a superpositionvoltage by superposition theory. The boost circuit includes a firstinput connected to the superposition voltage of the sampling-hold andintegrating circuit, a second input end is connected to a secondreference voltage, and an output end is connected to the illuminantchannel in the LED backlight module. The second voltage dividing circuitprovides a note voltage and the note voltage is connected to the secondinput end of the sampling-hold and integrating circuit and the boostcircuit, and the note voltage is calculated by the output voltage andthe second voltage dividing circuit by a voltage dividing theory. Thesuperposition voltage is calculated by the first voltage dividingcircuit of the sampling-hold and integrating circuit, the pulse highsignal and the note voltage by the superposition theory.

A LED backlight module connected to a PWM signal and the LED backlightmodule includes a LED backlight module made by a plurality of illuminantchannels and a constant current regulator. The LED backlight module ismade by a plurality of illuminant channels. The constant currentregulator includes a first input end connected to the illuminant channelof the LED backlight module, a second input end connected to the PWMsignal and an output end configured to output the PWM signal of theilluminant channel. The voltage converter includes a minimum voltageselector, a sampling-hold and integrating circuit, and a boost circuit.The minimum voltage selector includes an input end respectivelyconnected to a PWM signal of the illuminant channels and a plurality offirst reference voltages corresponding to the plurality of illuminantchannels, and an output end thereof outputting a pulse high signal atminimum conduction. The sampling-hold and integrating circuit includes afirst input end and a second input end, and the first input end isconnected to the pulse high signal of the minimum voltage selector andoutputs a superposition voltage. The boost circuit includes a firstinput connected to the superposition voltage of the sampling-hold andintegrating circuit, a second input end connected to a second referencevoltage, and an output end connected to the illuminant channel in theLED backlight module. The second voltage dividing circuit provides anote voltage and the note voltage is connected to the second input endof the sampling-hold and integrating circuit and the boost circuit, andthe note voltage is calculated by the output voltage and the secondvoltage dividing circuit by a voltage dividing theory. The superpositionvoltage is calculated by the first voltage dividing circuit of thesampling-hold and integrating circuit, the pulse high signal and thenote voltage by the superposition theory. The control device isconnected to the PWM signal and a plurality of adjusting loops outputtedby the constant current regulator and outputs a plurality of digitalsignals to the input end of the constant current regulator.

A sampling-hold and integrating circuit includes first differentialamplifier, a second differential amplifier and a first voltage dividingcircuit. The first differential amplifier includes a first input endconnected to an integrator and a second input end connected to an outputend of the first differential amplifier to form a feedback loop. Thesecond differential amplifier includes a first input end connected to anote voltage provided by the second voltage dividing circuit and asecond input end is connected to a output end of the second differentialamplifier. The first voltage dividing circuit is made by a plurality ofresistors, and includes one end connected to the output end of the firstdifferential amplifier and a second end connected to the output end ofthe second differential amplifier. The integrator is connected to thepulse high signal outputted by the output end of the minimum voltageselector at minimum conduction.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIG. 1A is a view illustrating a direct backlight module made byconventional LED;

FIG. 1B is a block diagram illustrating the DC-DC converter of a LEDbacklight module in prior art;

FIG. 1C is the equivalent circuit of an illuminant device in FIG. 1B;

FIG. 1D is another conventional equivalent circuit of an illuminantdevice;

FIG. 2 is a block diagram illustrating the LED backlight module in thepresent invention;

FIG. 3 is a system block diagram illustrating the DPWM modulation unitin the present invention;

FIG. 4 is a view illustrating the DPWM FSM in the present invention isdoing the digital encoding;

FIG. 5 is a view illustrating the circuit of the multi-task component inthe present invention;

FIG. 6 is a system block diagram of the voltage converter in the presentinvention;

FIG. 7 is a view illustrating the minimum select circuit in the presentinvention;

FIG. 8 is a circuit view illustrating the sampling-hold and integratingcircuit in the present invention; and

FIG. 9 is a signal view illustrating the PWM signal controls the LEDbacklight module in the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is an adjusting apparatus of the light emittingdiode (LED) backlight module, and more particularly is to provide themost suitable pulse width modulation (PWM) in each of the channels ofthe LED backlight module before driving the LED backlight module. Thetechnique description of the LED or the LED backlight module is based onthe prior art, so the detail description thereof is omitted herein. Thefollowing is the detailed description of the present invention, whichdescribes a method of fabricating an integral device of a biochipintegrated with micro thermo-electric elements and the apparatus, butthe detailed structure composition and the operating theory are notdiscussed. The portions relating to the conventional techniques arebriefly described, and the parts of the drawings are not proportionallydrafted. While embodiments are discussed, it is not intended to limitthe scope of the present invention. Except expressly restricting theamount of the components, it is appreciated that the quantity of thedisclosed components may be greater than that disclosed. Besides, in thefollowing paragraphs, those technique terms are replaced by Englishabbreviations. For example, light emitting diode is LED, pulse widthmodulation is PWM, input PWM signal is PWM_in and Dimming PWM is DPWM.

Now, please referring FIG. 2, it is a block diagram illustrating the LEDbacklight module in the present invention. As shown in FIG. 2, the LEDbacklight module 10 includes a voltage converter 100, a PWM controller200, a constant current regulator 300 connected to the PWM controller200 and a LED illuminant device 400 respectively connected to thevoltage converter 100 and the constant current regulator 300. Obviously,the LED illuminant 400 in the present invention is respectivelyconnected to the output end of the voltage converter 100 and the inputend of the constant current regulator 300, and a loop is generated fromthe input end of the voltage converter 100 to the LED illuminant device400 and the constant current regulator 300. The output end of thevoltage converter 100 is configured to provide a voltage control signaland is connected to several light channels of the LED illuminant device400 in parallel. Each of the first input end of the constant currentregulator 300 is connected to the PWM control signals. In addition, eachof the second inputs in the constant current regulator 300 is connectedto the light channel of the LED illuminant device 400. According to thecontrol method disclosed in the present invention, the PWM signal withdifferent phase and different duty cycle is able to drive the illuminantdevice between the light channels of the LED illuminant device 400.

Now, as shown in FIG. 2, the voltage converter 100 converts an inputvoltage (V_(in)) to be an higher output voltage (V_(out)) and thevoltage converter 100 is a DC-DC converter. The converted output voltageis transmitted to a LED illuminant device, such as a LED backlightmodule in LCD TV. The LED illuminant device 400 is made by several LEDcomponents 500 or several LED light channel 401. The LED light channelis made by several LED components 500 as shown in FIG. 1A. The LEDilluminant 400 in the present invention also includes Dimming PWMcontroller 200 configured to convert a PWM_in signal to be several DPWMsignals (DPWM channel, DPWM_ch) and the PWM_in signal is provided by thedisplay system with LED illuminant device 400 (such as the controllerprovided by the LCD TV). The PWM controller 200 includes a PWMmeasurement unit 210, an adjusting unit and a DPWM modulator 250. TheDPWM controller 200 transmits each of the digital DPWM signals to thefirst input of the constant current regulator 300 and the other input ofthe constant current regulator 300 is connected to one end of the LEDilluminant device 400. The output end of the voltage converter 100transmits the current in each channel to the LED illuminant device 400.Therefore, the PWM controller with adjusting function in the presentinvention is configured to convert the PWM signal to be the digitalsignal and the signal is processed by the adjusting unit 230 to be thecorresponding digital signal. Therefore, the PWM controller withadjusting function in the present invention can be embedded to be a chipby semiconductor process so as to control PWM analog signal.

Still referring to FIG. 2, the constant current regulator 300 isconnected to a predetermined number of feedback signals and theadjusting unit 230 of the DPWM controller 200 so as to form a currentcalibration handshake loop 310. In the present invention, in order tosimply the detail description, the predetermined number of feedbacksignal in the constant current regulator 300 of the present embodimentis three, and there are three feedback signals in each channel connectedto the adjusting unit 230 in the current calibration handshake loop 310in the present invention. Therefore, the adjusting unit 230 is going togenerate N channel adjusting signal Ch0_cal[2:0]˜ChN_cal[2:0], where[2:0] is represented that there are three feedback signals (3 bits) ineach channel. It should be noted that the current calibration hand shakeloop 310 in the present invention can include two feedback signals (theadjusting unit 230 generates N channel adjusting signalCh0_cal[1:0]˜ChN_cal[1:0]), four feedback signals (the adjusting unit230 generates N channel adjusting signal Ch0_cal[3:0]˜ChN_cal[3:0]) ormore than four feedback signals and it is not limited herein. In thepresent embodiment, the predetermined number of feedback signals isthree. Obviously, those adjusting signals are transmitted in digitalmethod.

When the LED illuminant device 400 in the present invention is turnedon, the current calibration handshake loop 310 transmits the threefeedback signals to the adjusting unit 230 and the adjusting unit 230generates N adjusting signals (Ch0_cal[2:0]˜ChN_cal[2:0]). The currentstatus of the LED components 500 in each channel or the LED string 401is transmitted to the adjusting unit 230 of the PWM controller 200 bythe constant current regulator 300. The adjusting unit 230 generates Nadjusting digital signals (Ch0_cal[2:0]˜ChN_cal[2:0]) and the Nadjusting digital signals are transmitted to the DPWM modulation unit250. The current status is that the bias status in each light channel(the LED component 500 in each channel or each LED string 401) isdifferent, and it is required to provide different current to drive.Especially when the PWM is used to save the power, it is necessary toprovide a proper driving current in accordance with the status in eachlight channel so as to avoid bad driving to cause the illuminant orcolor is not consistent.

According to the operation procedure of the current calibrationhandshake loop 310 in the previous chapter, the PWM measurement unit 210of the DPWM controller 200 will count the PWM_in signals to determinehow many bits are used to transmit the digital signal by the PWMmeasurement unit 210 and the digital signals are transmitted to the DPWMmodulation unit 250 to generate several DPWM control signals(DPWM_ch0˜DPWM_chN). The DPWM control signals are transmitted to theconstant current regulator 300. For example, when the time clock of theLED backlight module 10 is 20 MHz and the duty cycle of the PWM_insignal is 1 KHz, the PWM measurement unit 210 counts the PWM_in signals20000 times in accordance with the time clock of the LED backlightmodule 10. When the 20000 times are converted to be binary code, 15 bitsare used to shown the number of 20000 and represented byPWM_pulse[14:0].

Now, please referring to FIG. 3, it is a system block diagramillustrating the DPWM modulation unit in the present invention. As shownin FIG. 3, the DPWM modulation unit 250 includes a DPWM finite statemachine (DPWM FSM) 2510, a multiplexer 2530 and a waveform generator2550. The DPWM FSM 2510 will encode the 15 bits digital signal(PWM_pulse[14:0]) of the PWM measurement unit 210 in accordance with thePWM signal controlling requirement. The controlling requirement is goingto proportionally reduce the PWM_in duty cycle. For example, if thepreset controlling requirement is to reduce 0.4% of the PWM_in dutycycle for the light channel, the DPWM FSM 2510 will sequentiallytransmits 8 adjusted DPWM digital signals(Cal0_DPWM_pulse[14:0]˜Cal7_DPWM_pulse[14:0]) and each of the adjustedDPWM control is to reduce 0.4% of PWM_in. 9 adjusted DPWM digital signaltransmitted by the DPWM FSM 2510 is:

3 bits feedback signal adjusted digital signal PWM reducing ratio 000Cal0_DPWM_pulse[14:0] no adjusting 001 Cal1_DPWM_pulse[14:0] reducing 4%010 Cal2_DPWM_pulse[14:0] reducing 8% 011 Cal3_DPWM_pulse[14:0] reducing12% 100 Cal4_DPWM_pulse[14:0] reducing 16% 101 Cal5_DPWM_pulse[14:0]reducing 20% 110 Cal6_DPWM_pulse[14:0] reducing 24% 111Cal7_DPWM_pulse[14:0] reducing 28%

The digital signal corresponding to each DPWM FSM 2510 channel iscalculated as the following:

At first, if the 15 bits signal inputted by the PWM measurement unit 210is PWM_pulse[14:0]=101_1011_0111_0100, the 15 bits signal is convertedto be the decimal value: 23412.

Because the first adjusted digit Cal0_DPWM_pulse[14:0] in DPWM FSM 2510won't be adjusted, the 15 bits digital signal Cal0_DPWM_pulse[14:0]outputted by the DPWM FSM 2510 is 101_1011_0111_0100 and transmitted tothe multiplexer 2530 and the 15 bits digital signal is transmitted tothe multiplexer 2530.

Because the second channel digit Call_DPWM_pulse[14:0] of the DPWM FSM2510 is set to reduce 4% of PWM_in, the decimal calculation is23412/1.04=22512. (round of to the unit place). Because the divisioncannot be used in digital circuit to calculate the 4% reduced value, thesecond channel value is calculated by the DPWM FSM 2510 and thecalculation method is:

Each of the 15 bits digital signal 101_1011_0111_0100 included 1 istransformed to be the decimal value and each of the decimal values isdivided by 1.04. Because only digit number is 1 will include a realvalue position, it is:01_(—)1011_(—)0111_(—)0100=23412(decimalsystem)=16384+4096+2048+512+256+64+32+16+4(decimal system)then23412/1.04=(16384+4096+2048+512+256+64+32+16+4)/1.04=(16384/1.04)+(4096/1.04)+(2048/1.04)+(512/1.04)+(256/1.04)+(64/1.04)+(32/1.04)+(16/1.04)+(4/1.04)Now, each of the equations is calculated as the following:16384/1.04=6384−(16384*(1−(1/1.04)))=16384−630  (1)4096/1.04=4096−(4096*(1−(1/1.04)))=4096−158  (2)2048/1.04=2048−(2048*(1−(1/1.04)))=2048−79  (3)512/1.04=512−(512*(1−(1/1.04)))=512−20  (4)256/1.04=256−(256*(1−(1/1.04)))=256−10  (5)64/1.04=64−(64*(1−(1/1.04)))=64−2  (6)32/1.04=32−(32*(1−(1/1.04)))=32−1  (7)16/1.04=16−(16*(1−(1/1.04)))=16−1  (8)4/1.04=4−(4*(1−(1/1.04)))=4−0  (9)

Now,

$\begin{matrix}{{(1) + (2) + (3) + {\ldots\mspace{14mu}(9)\text{=>}{23412/1.04}}} = {23412 -}} \\{\left( {630 + 158 + 79 + 20 + 10 + 1 + 1} \right)} \\{= {22782 - \left( {158 + 79 + 20 + 10 + 1 + 1} \right)}} \\{= {22624 - \left( {79 + 20 + 10 + 1 + 1} \right)}} \\{= {22545 - \left( {20 + 10 + 1 + 1} \right)}} \\{= {22525 - \left( {10 + 1 + 1} \right)}} \\{= {22515 - \left( {1 + 1} \right)}} \\{= {22514 - 1}} \\{= 22513}\end{matrix}$

After 22513 is converted to be 101_0111_1111_0001, the 15 bits digitalsignal 101_0111_1111_0001 of the Call_DPWM_pulse[14:0] is transmitted tothe multiplexer 2530 by the DPWM FSM 2510.

Other channels are calculated to be 15 bits digital signals inaccordance with the calculation method described above.Cal4_DPWM_pulse[14:0]=23412/1.16=20183(decimal system)=100_(—)1110_(—)1101_(—)0111Cal5_DPWM_pulse[14:0]=23412/1.2=19510(decimal system)=100_(—)1100_(—)0011_(—)0110Cal6_DPWM_pulse[14:0]=23412/1.24=18881(decimal system)=100_(—)1001_(—)1100_(—)0001Cal7_DPWM_pulse[14:0]=23412/1.28=18291(decimal system)=100_(—)0111_(—)0111_(—)0011

The 2^(nd)˜8^(th) 15 bits digital signals calculated by the previousequations are transmitted to the multiplexer 2530. In addition, itshould be noted that when the DPWM FSM 2510 in the present invention isdoing digital decoding in accordance with the preset PWM signal controlmethod, 8 adjusting values are doing digital decoding at the same time,as shown in FIG. 4. Of course, the 8 adjusting values can also dodigital decoding sequentially, and it is not limited herein. Moreover,as the description above, the number N of the channels of the DPWM FSM2510 in the present invention can be 8 channels, 16 channels, 32channels or above and it is not limited herein. The alphabet N is onlyused to present the number of channels in the embodiments of the presentinvention.

Please refer to FIG. 3 now, when the DPWM FSM 2510 generates 8 adjustedDPWM digital encoding signals and transmits to the first input of themultiplexer 2530. The second input of the multiplexer 2530 is connectedto several adjusting signals (Ch0_cal[2:0]˜ChN_cal[2:0]) generated bythe adjusting unit 230.

The operation method of the multiplexer 2530 is shown in FIG. 5, and itis a circuit view of the multiplexer in the present invention. As shownin FIG. 5, the multiplexer 2530 is made by several circuit componentsand the circuit component is a multi-task selector in the presentembodiment. Moreover, as the description above, the number of thechannels of the multiplexer 2530 in the present invention can be 16channels, 32 channels or above and it is not limited herein. The firstinput in the multi-task selector is connected to the 8 DPWM signalstransmitted by the DPWM FSM 2510. There is a 15 bits digital signal ineach DPWM signal and the second input in the multi-task selector isconnected to the adjusting signal (Ch0_cal[2:0]˜ChN_cal[2:0]) generatedby the adjusting unit 230. Therefore, when the 3 loops of the currentcalibration handshake loop 310 are connected to the adjusting unit 230and the adjusting unit 230 generates 8 adjusting signals, each of thesecond inputs of the multi-task selector is connected to a adjustingsignal (Ch_cal[2:0]). The multiplexer will choose the best digitalencoding signal in 8 15 bits digital encoding signals according to theadjusting signal and transmits the best digital encoding signal to thefirst input of the pulse generating unit 2550.

Obviously, the multiplexer 2530 includes several channels by themulti-task selector. The number of the channels in the multiplexer 2530is determined by the LED quantity. For example, as the embodiment inFIG. 5, the multiplexer 2530 is configured to control N LEDs, and themultiplexer 2530 includes N channels formed by the N multi-taskselector. Each of the multi-task selector will choose the DPWM 15 bitsdigital signal in accordance with the adjusting signal (Ch_cal[2:0]) toreceive a best digital encoding signal (Ch_PWM_pulse[14:0]). The 15 bitsdigital encoding signal (Ch_PWM_pulse[14:0]) in the N channels istransmitted to the pulse generator 2550.

It should be noted that, in the present embodiment, the multiplexer 2530includes N output channels made by N multi-task selectors 2530. Thefirst input in each of the multi-task selectors is connected to the 8DPWM transmitted by the DPWM FSM 2510. The second input of themultiplexer 2530 is connected to the one of the N adjusting signalsgenerated by the adjusting unit 230. Therefore, when the multiplexer2530 is an output channel, the connection method is to sequentiallyconnect the 1^(st) to N^(th) multi-task selector with one adjustingsignal. When the multiplexer 2530 is in operation, each of themulti-task selectors will choose one the best digital encoding signal inaccordance with an adjusting signal to output. Therefore, when themultiplexer 253 includes N output channels, the 15 bits digital encodingsignal outputted in each of the channels could be the same or different,but the signal must be chosen from 8 15 bits digital signals in thefirst input end.

Now referring to FIG. 3, when the multiplexer 2530 chose 15 bits digitalencoding signal of the N channels, the 15 bits digital encoding signalis transmitted to the first input end of the pulse generator 2550. Thesecond input end of the pulse generator 2550 is connected to the 15 bitsdigital signal (PWM_pulse[14:0]) of the measurement unit 210. Accordingto the digital encoding signal(Ch0_DPWM_pulse[14:0]˜ChN_DPWM_pulse[14:0]) in N channels of the firstinput end and the 15 bits digital signal in the second input end, thepulse generator 2550 outputs N analog DPWM control signals (analog DPWMsignal DPWM_ch0˜DPWM chN) and transmits the analog DPWM control signalto the constant current regulator 300. When each of the analog DPWMcontrol signal is inputted to the constant current regulator 300, eachof the analog DPWM control signals is processed in the constant currentregulator 300 and the current in each channels is transmitted to one LEDilluminant device 400.

When the LED illuminant device 400 in the present invention is in theturn on procedure, a digital encoding signal (Ch_PWM_pulse[14:0]) ischosen between the N adjusting signal and the 8 15 bits digital signalsby the multiplexer 2530. The best 15 bits digital encoding signal istransmitted to the pulse generator 2550 to convert to be analog DPWMcontrol signal. The DPWM control signal device 200 outputs the DPWMcontrol signal to the constant current regulator 300. The main purposeis to transmit the current status in each channel of the LED componentor several LED strings 401 to the adjusting unit 230 of the PWM controldevice 200 by the constant current regulator 300. The adjusting unit 230will output N adjusting digital signal to the DPWM modulation unit 250.The current status is that the bias voltage in each illuminant channelis different (such as the LED component 500 in each channel or each LEDstring 401), so different currents are required to drive the illuminantchannel. When the PWM is used to save power energy, each illuminant isrequired to provide proper driving current to avoid the illuminant orcolor is not consistent because of bad driving.

Now, please referring to FIG. 6, it is a system block diagram of thevoltage converter in the present invention. As shown in FIG. 6, one endof the voltage converter 100 is connected to the pulse width modulationsignal (VLED) in each illuminant channels (ex: LED1-LED8). The DPWMcontrol signal outputted by the DPWM control signal device 200 istransmitted from the PWMI to the constant current regulator 300, and thepulse width modulation signal (VLED) in each illuminants is modulated bytransmitting to the constant current regulator 300 and the inputtedpulse width modulation signal so as to output the pulse width modulationsignal (such as VLED1-8) in each illuminant channel. Obviously, the DPWMsignal of the DPWM control signal device 200 in FIG. 3 is transmitted tothe constant current regulator 300 from the PWMI in FIG. 6.

The voltage converter 100 includes a boost circuit 110, a minimumvoltage selector 120, a sample-hold and integrating circuit 14, and anovervoltage protection voltage 144. The input end of the minimum voltageselector 120 is connected to the PWM signal (VLED1-8) and severalreference voltage (LED_ref1-8). The output end thereof is connected tothe minimum voltage signal (dVLED_min). The minimum voltage signal(dVLED_min) is transmitted to the sampling-hold and integrating circuit140 and a superposition voltage (Vsum) is generated by the superpositiontheory of the sampling-hold and integrating circuit 140. Therefore, thesuperposition voltage is transmitted to the boost circuit 110 andcompared with a reference voltage (Vref) to output a output voltage(Vout) to the LED illuminant device 400 so as to form a loop. Inaddition, the output voltage (Vout) is connected to the overvoltageprotection circuit 144. The overvoltage protection circuit 144 is madeby the series resistant R01 and R02. One end of the series resistant R01and R0 is connected to the output voltage (Vout) of the boost circuit110 and the other end is grounded. The node voltage (V_(ovp)) betweenthe series resistant R01 and R02 is calculated by dividing voltage. Thenode voltage (V_(ovp)) is feedback to the boost circuit 110 and thesample-hold and integrating circuit 140 and the output voltage (V_(out))is connected to a capacitance 147. When the PWM control signal isconductive, the output voltage (V_(out)) can provide the proper currentfor LED illuminant 400 and charge the capacitance 147. When the PWMcontrol signal is not conductive, the output voltage (V_(out)) is keptat a proper voltage in accordance with the capacitance 147.

FIG. 7 is a view illustrating the minimum select circuit in the presentinvention. As shown in FIG. 7, the minimum select circuit 120 includesseveral first comparators 1210 and a second comparator 1220 and thefirst input end in each of the first comparators 1210 is connected tothe PWM signal (VLED1-8) in each illuminant channel. The second inputend is connected to the reference voltage (VLED_ref1-8). The output endin each comparator 1210 will output a voltage difference value (dVLED)to the input end of the second comparator 1220. The second comparator1220 will output the minimum voltage signal (dVLED_min) in several inputvoltages. In the embodiment of the present invention, the referencevoltages (VLED_ref) can be respectively transmitted (such as VLED_ref_1;VLED_ref_2 . . . ) and are compared to the PWM signal (VLED_1, VLED_2 .. . ) in each channel so as to output the compared result to the secondcomparator 1220. The method to provide the reference voltage (VLED_ref)is not limited herein, and it all depends on the designer's requirement.

FIG. 8 is a circuit view illustrating the sampling-hold and integratingcircuit in the present invention. As shown in FIG. 8, the sampling-holeand integrating circuit 140 includes a first differential amplifier 141and the first input thereof is connected to an integrator 145 configuredto maintain the voltage inputted in the first input end of the firstdifferential amplifier 141 to be more than 0V. The second input end isfeedback to connect to the output end V1 of the first differentialamplifier 141. The output end V1 of the first differential amplifier 141is connected to a first voltage dividing circuit 142 formed by severalresistors. For example, in the present embodiment, the resistors R1, R2and R3 are together to form the first voltage dividing circuit 142 andR3 is connected to R1 and R2 in parallel. The first input end of thesecond differential amplifier 143 is connected to the note voltage(V_(ovp)) formed by over-voltage protection circuit 144 and the notevoltage (V_(ovp)) is the voltage protection circuit 144 feedback to thefirst input of the second differential amplifier 143. The second inputend is connected to the output end V2 of the second differentialamplifier 143. The output end V2 of the second differential amplifier143 is connected to the first dividing voltage 142.

In the embodiment of the sampling-hold and integrating circuit 140 ofthe present invention, the minimum voltage signal (dVLED_min) outputtedby the minimum voltage select circuit 120 is transmitted to theintegrator 145 of the sampling-hold and integrating circuit 140 and theintegrator 145 will raise the minimum voltage to be a holding voltage(V_(hold)). However, in a preferred embodiment, the gain of the firstdifferential amplifier 141 of the sampling-holding and integratingcircuit 140 is set to be 1 and the V_(hold)=V1 in the first differentialamplifier 141. The gain of the second differential amplifier 143 of theintegrator 140 is also set to be 1 and the Vovp=V2 in the seconddifferential amplifier. Obviously, the first dividing voltage 142 of thesampling-hold and integrating circuit 140 is able to get thesuperposition voltage (V_(sum)) in accordance with the holding voltage(V_(hold)) and the note voltage (Vovp) by the superposition theory,where:

$V_{sum} = \frac{\left\lbrack {\left( {R\; 1 \times R\; 3 \times V\; 2} \right) + \left( {R\; 2 \times R\; 3 \times V\; 1} \right)} \right\rbrack}{\left( {R\; 1 \times R\; 2} \right) + \left( {R\; 2 \times R\; 3} \right) + \left( {R\; 3 \times R\; 1} \right)}$

When the superposition voltage is calculated, it is transmitted to theboost circuit 110 in FIG. 6 and compared with the reference voltage(V_(ref)) to transmit an output voltage (V_(out)) by the boost circuit110. The output voltage (V_(out)) is connected to the over-voltageprotection circuit 144 and calculated to receive a note voltage(V_(ovp)) by the voltage dividing theory. The note voltage (V_(ovp)) isfeedback to the first input end of the second differential amplifier143. The superposition voltage (V_(sum)) is also the amplifieddifferential feedback voltage. The superposition voltage (V_(sum)) iscalculated to get the dividing voltage value of the output end V2 of thesecond differential amplifier 143, and the note voltage (V_(ovp)) formedby the over-voltage protection circuit 144 (the second voltage dividingcircuit) is determined, where

$V_{O\; V\; P} = {{V\; 2} = \frac{\left\lbrack {{V_{sum} \times \left( {\left( {R\; 1 \times R\; 2} \right) + \left( {R\; 2 \times R\; 3} \right) + \left( {R\; 1 \times R\; 3} \right)} \right)} - \left( {R\; 2 \times R\; 3 \times V\; 1} \right)} \right\rbrack}{R\; 1 \times R\; 3}}$

As shown in FIG. 6, the reference voltage (V_(ref)) in the boost circuit110 is designed by the requirement of the user. In a steady state, thereference voltage (V_(ref)) is equal to the superposition voltage(V_(sum)) and the note voltage of the second dividing voltage circuitis:

$V_{O\; V\; P} = {{V\; 2} = \frac{\left\lbrack {{V_{ref} \times \left( {\left( {R\; 1 \times R\; 2} \right) + \left( {R\; 2 \times R\; 3} \right) + \left( {R\; 1 \times R\; 3} \right)} \right)} - \left( {R\; 2 \times R\; 3 \times V_{hold}} \right)} \right\rbrack}{R\; 1 \times R\; 3}}$

As the equation above, when the reference voltage (V_(ref)) isdetermined, the note voltage (V_(ovp)) is changed in accordance with theholding voltage (V_(hold)). For example, when the holding voltage is ina rising stage, the note voltage (Vovp) is decreased and the outputvoltage (V_(out)) is decreased. When the holding voltage (V_(hold)) isin a descending stage, the note voltage is increased and the outputvoltage is increased (V_(out)). Therefore, when the reference voltage(V_(ref)) is set to be determined, the output voltage (V_(out)) is ableto adjust to be a better specification. For example, the output voltage(Vout) is set to be match the specification of the minimum voltage is 0(DVLED_min=0). The activation of the over-voltage protection circuit 144in the present embodiment won't be affected by the control method of theentire system.

Therefore, when the PWM signal is on in the duty cycle, each of theilluminant channels (401-408) in the LED backlight module 400 absorbsthe current from the output voltage (V_(out)). When the PWM signal isoff in the duty cycle, the boost circuit 110 is turned off and thevoltage required at each of the illuminant channels (401-408) isprovided by the capacitance 147. The output voltage would not be variedwhen the PWM signal is off at the duty cycle. Moreover, the voltageconverter 100 in the present invention can select a PWM signal with aminimum different value compared to the reference voltage in the PWMsignals of a plurality of the illuminant channel (401-408) and the PWMsignal is calculated by the sampling-hold and integrating circuit 140and the boost circuit 110 to output a output voltage (V_(out)).Obviously, the voltage converter 100 in the present invention cangenerate a proper output voltage (V_(out)) to drive the LED backlightmodule 400 in accordance with the PWM signals of a plurality of theilluminant channels (401-408) of the LED backlight module 400.

Now please referring to FIG. 2 and FIG. 9, FIG. 9 is a signal viewillustrating the PWM signal controls the LED backlight module in thepresent invention. As shown in FIG. 2, when the constant currentregulator 300 executed the controlling signals, several currents areoutputted to each of the illuminant channels (401-408) in the LEDbacklight module 400 and each of the illuminant channels (401-408) inthe LED backlight module 400 would output several modulated PWM signals(VLED1-8). Obviously, when the PWM signal is on in the duty cycle, eachof the illuminant channels (401-408) absorbs the currents from theoutput voltage (V_(out)), and the practical absorbing voltage is thecombination of the output voltage (Vout) an the PWM signal (VLED) ineach illuminant channel (401-408), as shown in FIG. 9. Because the biasvoltage in each of the illuminant channels (401-408) in the presentinvention is provided in accordance with the DPWM control signaloutputted by the DPWM control device 200 to the constant currentregulator 300. As the description above, the bias statues in each of theilluminant channels (401-408) can be different. Therefore, when the PWMsignal is used to save the power, the DPWM control device 200 in thepresent invention is used to provide proper driving current inaccordance with the status in each of the illuminant channels to avoidthe illuminant or color is not consistence because of unsuccessfuldriving. The sampling-hold and integrating circuit 140 in the presentinvention is used to provide an output voltage (V_(out)) generated bythe minimum voltage difference to each of the illuminant channels(401-408) of the LED illuminant device 400. Therefore, the PWMcontrolling device and the voltage converter 100 of the sampling-holdand integrating circuit 140 are used in the present invention to thecontrol loop of the bias status in each of the illuminant channels so asto provide different phase and different duty cycle of the PWM signal tothe LED backlight module 400 and the purpose of the power saving.Obviously, the control loop in the present invention with proper settingto transmit the PWM signal with the same phase, the same frequency andthe same duty cycle to the LED backlight module 400 is the preferredembodiment in the present invention.

The foregoing description is not intended to be exhaustive or to limitthe invention to the precise forms disclosed. Obvious modifications orvariations are possible in light of the above teachings. In this regard,the embodiment or embodiments discussed were chosen and described toprovide the best illustration of the principles of the invention and itspractical application to thereby enable one of ordinary skill in the artto utilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated. All suchmodifications and variations are within the scope of the invention asdetermined by the appended claims when interpreted in accordance withthe breadth to which they are fairly and legally entitled.

What is claimed is:
 1. A module unit with adjusting pulse widthfunctions and connected to a first digital signal and a plurality ofsecond digital signals, and the module unit comprises: a finite statemachine including an input end connected to the first digital signal andconfigured to encode the first digital signal by a predetermined controlrequirement to generate and output a plurality of third digital signalswith different encoding codes; a multiplexer made by a plurality ofcircuit components and including a first input end in each circuitcomponents connected to the third digital signal and a second input endin each circuit component connected to the second digital signal, and isconfigured to output a plurality of forth digital signals with differentencoding codes; and a pulse generator including a first input endconnected to the first digital signal and a second input end connectedto the forth digital signal, and is configured to convert the forthdigital signal to be a plurality of analog signals.
 2. The modulationunit of claim 1, wherein the predetermined control requirement is toproportionally decrease a valid cycle of the input PWM signal.
 3. Themodulation unit of claim 1, wherein the finite state machine isconfigured to generate the third digital signals by a parallel processmethod.
 4. The module unit of claim 1, wherein the circuit components ofthe multiplexer are multi-task selectors.
 5. A control device withadjusting pulse width function and is connected to an inputted pulsewidth modulation signal and a plurality of adjusting loops, and thecontrol unit comprises: a measurement unit configured to count the inputPWM signal, convert the input PWM signal to be a first digital signalwith a plurality of bits and output the first digital signal; anadjusting unit connected to the adjusting loops and configured togenerate a plurality of second digital signals with different encodingcodes; a module unit including an input end connected to the firstdigital signal and the second digital signal, and the first digitalsignal is encoded by a predetermined control requirement so as to outputa plurality of analog signals.
 6. The control device of claim 5, whereinthe predetermined control requirement is to proportionally decrease avalid cycle of the input PWM signal.
 7. The control device of claim 5,wherein the module unit is connected to the first digital signals andthe second digital signal and the module unit includes: a finite statemachine including an input end connected to the first digital signal andconfigured to encode the first digital signal by a predetermined controlrequirement to generate and output a plurality of third digital signalswith different encoding codes; a multiplexer made by a plurality ofcircuit components and including a first input end in each circuitcomponents connected to the third digital signal and a second input endin each circuit component connected to the second digital signal, and isconfigured to output a plurality of forth digital signal with differentencoding codes; and a pulse generator including a first input endconnected to the first digital signal and a second input end connectedto the forth digital signal, and is configured to convert the forthdigital signal to be a plurality of analog signals.
 8. The controldevice of claim 7, wherein the circuit components of the multiplexer aremulti-task selectors.
 9. A backlight module, comprising: a voltageconverter configured to convert a input voltage (Vin) to be a higheroutput voltage (Vout); a control device connected to a input PWM signaland a plurality of adjusting loop, and the control device includes: ameasurement unit configured to count the input PWM signal, convert theinput PWM signal to be a first digital signal with a plurality of bitsand output the first digital signal; an adjusting unit connected to theadjusting loops and configured to generate a plurality of second digitalsignals with different encoding codes; a module unit including an inputend connected to the first digital signal and the second digital signal,and the first digital signal is encoded by a predetermined controlrequirement so as to output a plurality of analog signals; a currentregulator connected to the analog signals outputted by the controldevice; a plurality of adjusting loops connected to the adjusting unitand the current regulator; and a LED illuminant device made by aplurality of LED illuminant unit, and each of the illuminant units isconnected to the analog signal.
 10. The control device of claim 9,wherein the module unit is connected to the first digital signals andthe second digital signal and the module unit includes: a finite statemachine including an input end connected to the first digital signal andconfigured to encode the first digital signal by a predetermined controlrequirement to generate and output a plurality of third digital signalswith different encoding codes; a multiplexer made by a plurality ofcircuit components and including a first input end in each circuitcomponents connected to the third digital signal and a second input endin each circuit component connected to the second digital signal, and isconfigured to output a plurality of forth digital signal with differentencoding codes; and a pulse generator including a first input endconnected to the first digital signal and a second input end thereofconnected to the forth digital signal, and is configured to convert theforth digital signal to be a plurality of analog signals.
 11. A voltageconverter including one end connected to a constant current regulatorand the constant current regulator is connected to a PWM signal of theilluminant channels, wherein the voltage converter is characteristic by:a minimum voltage selector including an input end respectively connectedto a PWM signal of the illuminant channels and a plurality of firstreference voltages corresponding to the plurality of illuminantchannels, and an output end outputting a minimum voltage signal; asampling-hold and integrating circuit including a first input end and asecond input end, and the first input end is connected to the minimumvoltage signal of the minimum voltage selector and outputs ansuperposition voltage; and a boost circuit including a first inputconnected to the superposition voltage of the sampling-hold andintegrating circuit, a second input end connected to a second referencevoltage, and an output end connected to the illuminant channel in theLED backlight module; wherein the second voltage dividing circuitprovides a note voltage and the note voltage is connected to the secondinput end of the sampling-hold and integrating circuit and the boostcircuit, and the note voltage is calculated by the output voltage andthe second voltage dividing circuit by a voltage dividing theory; andwherein the superposition voltage is calculated by the first voltagedividing circuit of the sampling-hold and integrating circuit, theminimum voltage signal and the note voltage by superposition theory. 12.The voltage converter of claim 11, wherein the sampling-hold andintegrating circuit includes: a first differential amplifier including afirst input end connected to an integrator and a second input endconnected to an output end of the first differential amplifier to form afeedback loop; a second differential amplifier including a first inputend connected to a note voltage provided by the second voltage dividingcircuit and a second input end connected to a output end of the seconddifferential amplifier; and a first voltage dividing circuit made by aplurality of resistors, and includes one end connected to the output endof the first differential amplifier and a second end connected to theoutput end of the second differential amplifier; wherein the integratoris connected to the minimum voltage signal outputted by the output endof the minimum voltage selector at minimum conduction.
 13. The voltageconverter of claim 12, wherein the gain of the first differentialamplifier and the gain of the second differential amplifier are
 1. 14.The voltage converter of claim 12, wherein the output voltage of thefirst differential amplifier is larger than 0V.
 15. A LED backlightmodule connected to a PWM signal and the LED backlight module comprises:a LED backlight module made by a plurality of illuminant channels; aconstant current regulator including a first input end connected to theilluminant channel of the LED backlight module, a second input endconnected to the PWM signal and an output end configured to output thePWM signal of the illuminant channel; a voltage converter includes: aminimum voltage selector, and an input end is respectively connected toa PWM signal of the illuminant channels and a plurality of firstreference voltages corresponding to the plurality of illuminantchannels, and an output end thereof outputs a minimum voltage signal atminimum conduction; a sampling-hold and integrating circuit including afirst input end and a second input end, and the first input end isconnected to the minimum voltage signal of the minimum voltage selectorand outputs a superposition voltage; a boost circuit including a firstinput connected to the superposition voltage of the sampling-hold andintegrating circuit, a second input end connected to a second referencevoltage, and an output end connected to the illuminant channel in theLED backlight module; wherein the second voltage dividing circuitprovides a note voltage and the note voltage is connected to the secondinput end of the sampling-hold and integrating circuit and the boostcircuit, and the note voltage is calculated by the output voltage andthe second voltage dividing circuit by a voltage dividing theory; andthe superposition voltage is calculated by the first voltage dividingcircuit of the sampling-hold and integrating circuit, the minimumvoltage signal and the note voltage by an superposition theory; acontrol device connected to the PWM signal and a plurality of adjustingloops outputted by the constant current regulator and outputs aplurality of digital signals to the input end of the constant currentregulator.
 16. The backlight module of claim 15, wherein thesampling-hold and integrating circuit includes: a first differentialamplifier including a first input end connected to an integrator and asecond input end connected to an output end of the first differentialamplifier to form a feedback loop; a second differential amplifierincluding a first input end connected to a note voltage provided by thesecond voltage dividing circuit and a second input end connected to aoutput end of the second differential amplifier; a first voltagedividing circuit made by a plurality of resistors, and includes one endconnected to the output end of the first differential amplifier and asecond end connected to the output end of the second differentialamplifier; wherein the integrator is connected to the minimum voltagesignal outputted by the output end of the minimum voltage selector atminimum conduction.
 17. The voltage converter of claim 16, wherein thegain of the first differential amplifier and the gain of the seconddifferential amplifier are
 1. 18. The backlight module of claim 16,wherein the control device includes: a measurement unit configured tocount the input PWM signal, convert the input PWM signal to be a firstdigital signal with a plurality of bits and output the first digitalsignal; an adjusting unit connected to the adjusting loops and generatesa plurality of second digital signals with different encoding codes; anda module unit including an input end connected to the first digitalsignal and the second digital signal, and the first digital signal isencoded by a predetermined control requirement to output a plurality ofanalog signals.
 19. The backlight module of claim 18, wherein the moduleunit is connected to the first digital signals and the second digitalsignal, and wherein the module unit includes: a finite state machineincluding an input end connected to the first digital signal andconfigured to encode the first digital signal by a predetermined controlrequirement to generate and output a plurality of third digital signalswith different encoding codes; a multiplexer made by a plurality ofcircuit components and includes a first input end in each circuitcomponents is connected to the third digital signal and a second inputend in each circuit component is connected to the second digital signal,and is configured to output a plurality of forth digital signal withdifferent encoding codes; and a pulse generator including a first inputend connected to the first digital signal and a second input end thereofis connected to the forth digital signal, and is configured to convertthe forth digital signal to be a plurality of analog signals.
 20. Thebacklight module of claim 15, further including a capacitance connectedthe note voltage.